Co-design for Low Warpage and High Reliability in Advanced Package yvith TSVFree Interposer (TFI)

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Co-design for Low Warpage and High Reliability in Advanced Package yvith TSVFree Interposer (TFI)
Title:
Co-design for Low Warpage and High Reliability in Advanced Package yvith TSVFree Interposer (TFI)
Journal Title:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC)
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Publication Date:
30 May 2017
Citation:
Abstract:
TSV-Free Interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. Co-design modelling methodology is established for TFI technology with considering wafer process, package assembly and package/board level reliability and thermal performance to optimize structure design, wafer process, assembly process and material selection. Experimental results are used for validating warpage modelling results. Through wafer level modelling, suitable carrier wafer and EMC materials are recommended to control wafer warpage less than 2mm. Effects of package substrate coefficient of thermal expansion (CTE) and stiffener on assembly induced package warpage are simulated to reduce package warpage. The recommended materials and geometry design based on reliability are aligned with that from wafer and package warpage simulation results. The final test vehicle (TV) design and material selection are determined based on co-design modelling results for achieving successful TFI wafer process and package assembly process and long term package/board level reliability.
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(c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
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