J. B. Lee, J. L. Aw and M. W. Rhee, "3-D TSV Six-Die Stacking and Reliability Assessment of 20- $mu$ m-Pitch Bumps on Large-Scale Dies," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 1, pp. 33-38, Jan. 2017. doi: 10.1109/TCPMT.2016.2628372
Abstract:
3-D integration typically involves multiple chips stacking with large numbers of interconnections within each chip. There are several fundamental technology challenges that need to be addressed in order to realize 3-D integration, such as Cu through-silicon via (TSV) expansion, transistor degradation or open failures on Cu contamination, microbump stress, and so on. The reliability issues on TSV and microbumps are very
critical not only for a stacked chip package, but also during wafer-level processes. In this paper, the authors successfully stacked six chips with a thickness of 50 μm and assessed their reliability. Each chip consists of 122 054 bumps with a bump diameter of 10 μm and a pitch of 20 μm. These bumps were built directly on TSVs, which have a diameter of 5 μm. Measured electrical resistance is well matched with calculated electrical
resistance. Finally, this paper presents the reliability results of the 3-D IC packages that are embedded in molding compound.
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