0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization

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0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization
Title:
0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization
Journal Title:
IEEE Journal of Solid-State Circuits
Keywords:
Publication Date:
13 April 2016
Citation:
A. T. Do, Z. C. Lee, B. Wang, I. J. Chang, X. Liu and T. T. H. Kim, "0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization," in IEEE Journal of Solid-State Circuits, vol. 51, no. 6, pp. 1487-1498, June 2016.
Abstract:
In sub/near-threshold operation, SRAMs suffer from considerable bitline swing degradation when the data pattern of a column is skewed to ‘1’ or ‘0’. The worst scenarios regarding this problem occur when the currently read SRAM cell has different data compared to the rest of the cells in the same column. In this work, we overcome this challenge by using a column-based randomization engine (CBRE). This CBRE circuit randomizes data stored to SRAM. This makes distribution of “1” and “0” in each column close to 50%, significantly increasing bitline swing. To further improve the bitline swing, we employ bitline boost biasing and dynamic bitline keeper schemes. Based on the mentioned techniques, we fabricated a 256 rows×128 columns (32Kb) 8T SRAM array in 65 nm CMOS technology. In our silicon measurement, the SRAM array shows successful 200 mV operation at room temperature, where energy consumption and access time are 1 pJ and 2.5 s, respectively.
License type:
PublisherCopyrights
Funding Info:
Description:
(c) 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
ISSN:
0018-9200
1558-173X
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