A Low Complexity and High Throughput MIMO Detection VLSI Design for MIMO-OFDM Systems

A Low Complexity and High Throughput MIMO Detection VLSI Design for MIMO-OFDM Systems
Title:
A Low Complexity and High Throughput MIMO Detection VLSI Design for MIMO-OFDM Systems
Other Titles:
2016 IEEE 83rd Vehicular Technology Conference (VTC Spring)
DOI:
10.1109/VTCSpring.2016.7504077
Publication Date:
15 May 2016
Citation:
Z. Cai, Y. H. Wang and S. Chattong, "A Low Complexity and High Throughput MIMO Detection VLSI Design for MIMO-OFDM Systems," 2016 IEEE 83rd Vehicular Technology Conference (VTC Spring), Nanjing, 2016, pp. 1-5. doi: 10.1109/VTCSpring.2016.7504077
Abstract:
This paper presents a linear Minimum Mean Square Error (MMSE) MIMO Detector design for MIMO-OFDM systems based on Application-Specific Instrument-set Processor (ASIP). As part of the IEEE 802.11ac-compliant PHY baseband transceiver, the proposed MIMO detector offers low latency, high throughput with efficient resource utilization. The design has been synthesized with TSMC 40 nm CMOS technology, the logic gate count for each QRD engine is about 245 K gates. It is able to support 20/40/80MHz bandwidth and up to 4 spatial streams. Detection latency for 80 MHz VHT mode (234 data sub-carriers) is 750 ns.
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PublisherCopyrights
Funding Info:
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