R. Weerasekera et al., "An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate," in IEEE Transactions on Electron Devices, vol. 63, no. 3, pp. 1182-1188, March 2016. doi: 10.1109/TED.2016.2522501
Abstract:
Through Silicon Via (TSV) is an integral part of 2.5D IC technology leveraged for multi-chip heterogeneous
integration achieving shorter interconnects, faster speed and lower power consumption in state-of-the-art circuit systems. These 2.5D ICs use a silicon substrate where there are no ground contacts unlike traditional 2D ICs or 3D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction methodology. Therefore, in this paper an analytical capacitance model for TSVs in a 2.5D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5D IC parasitic extraction framework in addition to design robust grounding schemes such that TSV-to-TSV crosstalk coupling in an entire 2.5D IC would be minimal even with floating silicon substrate. It is shown that regularly distributed large number of Power and Ground (P/G) TSVs provide an effective shield for TSV-to-TSV crosstalk coupling and are highly recommended in 2.5D ICs.
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