Dynamic Write-Level and Read-Level Signal Design for MLC NAND Flash Memory

Dynamic Write-Level and Read-Level Signal Design for MLC NAND Flash Memory
Title:
Dynamic Write-Level and Read-Level Signal Design for MLC NAND Flash Memory
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9th IEEE/IET International Symposium on COMMUNICATION SYSTEMS NETWORKS & DIGITAL SIGNAL PROCESSING (CSNDSP'14)
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Publication Date:
23 July 2014
Citation:
C. A. Aslam, Y. L. Guan and K. Cai, "Dynamic write-level and read-level signal design for MLC NAND flash memory," Communication Systems, Networks & Digital Signal Processing (CSNDSP), 2014 9th International Symposium on, Manchester, 2014, pp. 336-341.
Abstract:
In this paper, we propose dynamic write-level and read-level voltage scheme for MLC NAND flash memory. We study the characteristics of flash channel which can be modeled as mixture of Uniform and Exponential distribution. Since this channel shows non-stationary behavior , we present probability of error analysis and introduce the concept of dynamically adjusting the verify-level (write-level) and quantization-level (readlevel) voltage values over varying flash channel. The proposed dynamic voltage based method outperforms fixed verify-level voltage scheme. We demonstrate improvements in bit-error-rate (BER) performance and cell storage capacity for the proposed signal design scheme.
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