CRC Codes for Short Control Frames in IEEE 802.11ah

CRC Codes for Short Control Frames in IEEE 802.11ah
Title:
CRC Codes for Short Control Frames in IEEE 802.11ah
Other Titles:
Vehicular Technology Conference (VTC Fall), 2014 IEEE 80th
DOI:
10.1109/VTCFall.2014.6965925
Publication Date:
14 September 2014
Citation:
Choo, Li Chia; Lei, Zander, "CRC Codes for Short Control Frames in IEEE 802.11ah," Vehicular Technology Conference (VTC Fall), 2014 IEEE 80th , vol., no., pp.1,5, 14-17 Sept. 2014 doi: 10.1109/VTCFall.2014.6965925
Abstract:
In the new IEEE 802.11ah standard, a CRC code of 4 parity bits provides error detection for the SIG field of length 36 or 48 bits, giving rise to a significant performance penalty, which may be acceptable if there is an additional 32-bit Frame Check Sequence check on the payload in layer 2. However, in 802.11ah, there exist new Medium Access Control (MAC) control frames which are Null Data Packets (NDPs), which squeeze all critical information into the SIG field, and do not contain any payload at all. Hence, error checking is solely on CRC-4. These NDPs signal critical control functions in 802.11ah, and will affect MAC performance and energy consumption greatly if false positives occur. To achieve better performance, we propose that the number of parity bits be increased, and give the generator polynomials that achieve the improved performance. For the best performance-compatibility trade-off, an existing IEEE 802.11 CRC-8 generator can be used; the number of parity bits increased can be kept to 2, with a moderate performance gain, which can be achieved by a CRC-6 generator. Further, if the current generator and NDP control frame formats are fixed, but have some essential information bits to be received with high probability that they are correct, we may nest an inner CRC code to increase the error detection performance of the essential bits. For the inner code, an existing IEEE 802.11 CRC-8 generator can be used with a loss of 8 non-essential bits. We also propose an inner CRC-4 generator for a moderate performance gain and minimal loss of non-essential bits, and inner CRC-6 generators for enhanced performance.
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