Static Analysis Driven Cache Performance Testing

Static Analysis Driven Cache Performance Testing

2013 IEEE 34th Real-Time Systems Symposium

10.1109/RTSS.2013.39

https://doi.org/10.1109/rtss.2013.39

Abhijeet Banerjee, Sudipta Chattopadhyay, Abhik Roychoudhury

31 January 2014

Banerjee, A., Chattopadhyay, S., & Roychoudhury, A. (2013). Static Analysis Driven Cache Performance Testing. 2013 IEEE 34th Real-Time Systems Symposium. doi:10.1109/rtss.2013.39

Real-time, embedded software are constrained by several non-functional requirements, such as timing. With the ever increasing performance gap between the processor and the main memory, the performance of memory subsystems often pose a significant bottleneck in achieving the desired performance for a real-time, embedded software. Cache memory plays a key role in reducing the performance gap between a processor and main memory. Therefore, analyzing the cache behaviour of a program is critical for validating the performance of an embedded software. In this paper, we propose a novel approach to automatically generate test inputs that expose the cache performance issues to the developer. Each such test scenario points to the specific parts of a program that exhibit anomalous cache behaviour along with a set of test inputs that lead to such undesirable cache behaviour. We build a framework that leverages the concepts of both static cache analysis and dynamic test generation to systematically compute the cache-performance stressing test inputs. Our framework computes a test-suite which does not contain any false positives. This means that each element in the test-suite points to a real cache performance issue. Moreover, our test generation framework provides an assurance of the test coverage via a well-formed coverage metric. We have implemented our entire framework using Chronos worst case execution time (WCET) analyzer and LLVMcompiler infrastructure. Several experiments suggest that our test generation framework quickly converges towards generating cache-performance stressing test cases. We also show the application of our generated test-suite in design space exploration and cache performance optimization.

Publisher Copyright

This research / project is supported by the Agency for Science, Technology and Research - Public Sector Funding
Grant Reference no. : 1121202007

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https://oar.a-star.edu.sg/communities-collections/articles/11473

1052-8725

978-1-4799-2006-8

Institute for Infocomm Research