http://oar.a-star.edu.sg:80/jspui/handle/123456789/113 Sat, 24 Jun 2017 19:28:52 GMT 2017-06-24T19:28:52Z http://oar.a-star.edu.sg:80/jspui/handle/123456789/2114 Title: Drop Impact Reliability Test and Failure Analysis for Large Size High Density FOWLP Package on Package Authors: Chen, Zhaohui; Che, Faxing; Ding, Mian Zhi; Ho, David Soon Wee; Chai, Tai Chong; Srinivasa, Vempati Abstract: Drop test reliability of the 20 mm x 20 mm RDL-first FOWLP on bottom and 8 mm x 8 mm WLCSP on top for Package on Package (PoP) test vehicle was validated by the experimental testing in this paper. The results show that the built up PoP test vehicle can pass 30 times of drop impact test and some samples can pass 200 times drop impact test with the loading of 1500 G/0.5 ms. The failure mechanisms of Cu pad peeling off, cracking of dielectrics and Cu trace on the bottom RDL-first FOWLP and crack on package corner solder joints of top WLCSP were identified by cross section observation. The peeling stress level on the solder joint and dielectrics layer were investigated by the dynamic explicit nonlinear drop impact simulation. Description: (c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. Tue, 30 May 2017 00:00:00 GMT http://oar.a-star.edu.sg:80/jspui/handle/123456789/2114 2017-05-30T00:00:00Z http://oar.a-star.edu.sg:80/jspui/handle/123456789/2113 Title: Study of C2W Bonding Using Cu Pillar with Side-wall Plated Solder Authors: Xie, Ling; Wickramanayaka, Sunil; Sekhar, Vasarla Nagendra; Cereno, Daniel Ismael Abstract: Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as it contains no intermetallic compound as compared to Cu Solder Bump. However, Cu-Cu interconnect required stringent requirements such as Cu bump surface topography, flatness, uniformity and clean bonding surface. In this paper, a novel Cu-Cu interconnects is illustrated with the use of solder layer surrounding the side wall of the copper pillar. The solder layer offered a possibility of temporary tacking the chip on the wafer and then formed the interconnects through the use of gang bonder. With the tacking and gang bonding process, a higher throughput process can be realized and actively adopted by industry as it offers lower cost of assembly. Description: (c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. Tue, 30 May 2017 00:00:00 GMT http://oar.a-star.edu.sg:80/jspui/handle/123456789/2113 2017-05-30T00:00:00Z http://oar.a-star.edu.sg:80/jspui/handle/123456789/2112 Title: High-band AlN Based RF-MEMS Resonator for TSV integration Authors: Wang, Nan; Zhu, Yao; Sun, Chengliang; Yu, Mingbin; Chua, Gengli; Merugu, Srinivas Abstract: This paper reports two types of in-house fabricated aluminium nitride (AIN) based piezoelectric resonators, namely the thickness mode resonator and the Lamb-wave mode resonator, which are capable to be integrated with Through Silicon Via (TSV) technology, forming the basis of advanced filters, duplexers and multiplexers. Both types of the resonators, which are fabricated using a CMOS compatible platform, consist of a layer of 1μm thick piezoelectric layer and two layers of molybdenum (Mo) electrodes covering the top and the bottom surface of the AIN layer. Resonant frequencies above 2GHz, as well as motional impedance less than 10ohm, are obtained when the fabricated resonators are connected directly to the 50ohm terminations of a network analyzer, making both types of resonators suitable for high-band LTE applications. Furthermore, negligible performance drift was observed for both types of resonators fabricated upon undergoing accelerated thermal cycling test, indicating the superior reliability and long-term stability of the fabricated AIN based MEMS resonators and showing their great potential for communications applications in the automotive industry, where reliability and long-term stability is a key requirement for device performance. Description: (c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. Tue, 30 May 2017 00:00:00 GMT http://oar.a-star.edu.sg:80/jspui/handle/123456789/2112 2017-05-30T00:00:00Z http://oar.a-star.edu.sg:80/jspui/handle/123456789/2111 Title: Process and Reliability of Large Fan-Out Wafer Level Package based Package-on-Package Authors: Rao, Vempati Srinivasa; Chong, Chai Tai; Ho, David; Zhi, Ding Mian; Choong, Chong Ser; Lim, Sharon PS; Ismael, Daniel; Liang, Ye Yong Abstract: This paper presents, the development of large multi-chip fan-out wafer level package (FOWLP) based Package-on-Package (PoP) using mold-First FOLWP integration flow for mobile applications. As part of this development, conventional mold-First FOWLP wafer reconstruction process has been optimized and selected key materials to overcome the challenges such as die shift, die protrusion, warpage. Fine pitch multi-layer RDL of LW/LS of 5μm/5μm fabrication, through mold via (TMV) formation, thin wafer handling for backside RDL and PoP assembly processes were also optimized. TMV process using laser drilling and sidewall plated Cu with polymer filling has been demonstrated. Using these optimized processes multi-chip FOWLP of 15 mm x 15 mm with double side RDL and high I/O count ~1360 I/Os at 400μm pitch was successfully demonstrated. Assembly process flow was optimized for PoP assembly on test boards, and build the PoP samples for reliability testing. FOWLP PoP samples were passed component level tests like MST L1, MST L3, HAST, MST L1+TC and board level tests 500 TCOB cycles and 30 drops of board level drop test. Failure analysis was carried out using CSAM, cross-sectioning and SEM. Reliability tests and failure analysis results will be presented. Description: (c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. Tue, 30 May 2017 00:00:00 GMT http://oar.a-star.edu.sg:80/jspui/handle/123456789/2111 2017-05-30T00:00:00Z